The present invention relates to the field of semiconductor device manufacturing, and more particularly, to the use of offset spacers during the formation of a semiconductor device.
As the minimum feature size in semiconductor integrated circuits shrinks, the distance between the source and the drain regions becomes smaller. The reduced spacing between the source and drain regions for the field-effect transistors (FETs) results in short channel effects such as punch-through, reduced source-to-drain breakdown voltage, reduced threshold voltage (Vt), and increased sub-threshold swing. To relieve the short channel effects, the semiconductor industry is constantly optimizing the fabrication processes for MOSFET devices. Current trends in VLSI fabrication of CMOS devices are toward reducing the junction depth of the source/drain regions because shallow junctions reduce encroachment of the source/drain depletion regions into the channel.
Advances in semiconductor processing technology have reduced channel lengths to well below 0.25 xcexcm. At these sizes, any loss of effective channel length can be costly in terms of lowering the breakdown voltage of a transistor. Accordingly, limiting the lateral diffusion of the source/drain impurities is increasingly important.
A halo implant, also called a xe2x80x9cpocket implantxe2x80x9d, can limit the lateral diffusion of the source and drain impurities. The halo implants impurities have a conductivity type opposite to that of the source and drain. Usually, the halo implant comes after defining the gate and before the source/drain diffusion. Due to the masking effect, the halo implant typically exhibits peak impurity concentration near the source/drain regions. To impede vertical diffusion of source/drain impurities, the implant energy for the halo implant should be carefully chosen so that the halo depth away from the peak is greater than the depth of the source/drain implant.
In order to reduce the overlap capacitance between the gate electrode and the drain, and thereby provide better AC performance for the transistor, it is desirable to separate the halo and the extension. Accordingly, offset spacers have been employed that are formed on the sides of a gate electrode. By forming a halo, followed by the formation of an offset spacer on the sidewalls of gate electrode, and then formation of the source drain extensions, the halo is physically located in front of the extension. Use offset spacers makes the effective channel length longer for a given physical channel length.
In the formation of offset spacers, a dielectric layer is typically deposited over the substrate and a gate electrode. An anisotropic etch is performed to clear the substrate on top of the gate electrode of the dielectric layer while leaving a portion of the dielectric layer on the gate sidewalls. This portion of the dielectric layer remaining on the gate sidewalls forms the offset spacer. Materials that have been described for use as the offset spacers includes silicon oxide and silicon nitride. Once the offset spacer is formed, a source/drain extension implant is performed using the offset spacer as a mask. Continued processing steps include the formation of sidewall spacers over the offset spacers followed by deep source/drain implants.
The formation of the offset spacers in the above-described manner creates a problem in that the anisotropic etching gouges the silicon substrate caused by overetching of the dielectric layer from which the offset spacers are formed. This situation is depicted schematically in FIGS. 1 and 2. In FIG. 1, a substrate 10 has a gate electrode 12 on its surface. A dielectric layer 14 covers the substrate 10 and the gate electrode 12. An anisotropic etching is performed that removes the dielectric material 14 from the substrate to form the offset spacer 16. However, a recess 18 is also formed by the gouging of the substrate 10 caused by the overetching, since it is difficult to stop on silicon in anisotropic etching processes. The formation of the recess 18, especially in the source/drain extension area is a concern This is because silicon gouging is equivalent to increasing junction depth, which is undesirable as shallow depth junctions are sought after in today""s technologies. Also, the overlap capacitance is adversely affected by the gouging created during offset spacer creation.
There is a need for a method of forming a semiconductor device with offset spacers in a manner that prevents gouging of the silicon substrate during the etching of the dielectric layer that forms the offset spacers.
These and other needs are met by embodiments of the present invention which provide a method of forming a semiconductor device, comprising the steps of forming a gate electrode on substrate and forming a polysilicon reoxidation layer over the substrate and the gate electrode. A nitride layer is deposited over the polysilicon reoxidation layer. The nitride is anisotropically etched, with this etching stopping on the polysilicon reoxidation layer to form nitride offset spacers on the gate electrode. The use of the polysilicon reoxidation layer as an etch stop layer during the formation of the nitride offset spacers prevents the gouging of the silicon substrate in accordance with embodiments of the present invention. The very thin polysilicon reoxidation layer may be left on the substrate, and implantation may controllably and reliably be made through the remaining polysilicon reoxidation layer to form the source/drain extensions and source/drain regions. Alternatively, the polysilicon reoxidation layer may be removed by a wet etch, without creating the gouging normally associated with dry etching of a dielectric layer.
The earlier cited needs are also met by embodiments of the present invention which provide a method of performing a semiconductor device with halo implants, comprising the steps of forming a gate electrode on a substrate and forming an etch stop layer on the substrate. A nitride layer is formed on the substrate and on the gate electrode. The nitride layer is etched to form offset spacers on the gate electrode, with the etching stopping on the etch stop layer.